1. Field
Exemplary embodiments of the present invention relate to a technology for designing a semiconductor integrated circuit, and more particularly, to a redundant fuse circuit of a semiconductor memory device.
2. Description of the Related Art
A semiconductor integrated circuit includes a lot of circuits having the same pattern, and it includes a redundancy circuit for making up for a failure so that the semiconductor integrated circuit may be used as a normal product although it includes a circuit having failure according to procedural variable.
In particular, one memory chip includes a great deal of memory cells integrated therein. If there is any one memory cell including a failure among the memory cells, the memory chip is regarded as a defective chip and abandoned.
As more and more memory cells are integrated in a chip of a limited dimensions along the industrial tendency of high integration of a semiconductor integrated circuit, even one failure in any one cell makes the memory chip a defective chip and. In this case, the number of memory chips to be abandoned will increase and thus economical efficiency in the production of a semiconductor memory device is deteriorated.
To overcome the problem, a typical semiconductor memory device includes a fuse circuit and a redundant cell array. The fuse circuit includes a plurality of fuses that are formed of a metallic material. The fuse circuit substitutes a failure cell with a redundant cell during a repair process according to whether a fuse is blown or not. The redundant cell array and the fuse circuit are fabricated during a semiconductor device fabrication process. During a repair process, the redundant cell array and the fuse circuit substitutes a failure memory cell, which is decided having a failure, with a redundant cell, and the repair process is performed in such a manner that a fuse formed of a metallic material is cut off with a laser beam.
FIG. 1 illustrates an arrangement of a core region of a typical semiconductor memory device.
Referring to FIG. 1, the semiconductor memory device includes a cell array 100 where a plurality of memory cells that are selected based on a row address and a column address are regularly arrayed. Also, the semiconductor memory device includes a column selection line driver 110 for selecting and driving a column, which is a bit line, corresponding to the column address. Also, a word line driver for selecting and driving a row, which is a word line, is required but the part of columns will be described, herein.
As described before, the cell array 100 of the semiconductor memory device includes a redundant cell array for substituting a failure cell with a redundant cell. To be specific, a column redundant circuit 120 for programming the column information of a failure cell and, when the corresponding column address is inputted, substituting a failure column with a redundant column is disposed under the cell array 100 and the column selection line driver 110.
The column redundancy circuit 120 includes an array formed of a plurality of unit redundant fuse circuits. Each of the unit redundant fuse circuits includes a fuse 122, a fuse latch 124, and comparison logic 126. The fuse 122 programs the column address of a failure cell. The fuse latch 124 senses and stores the blowing state of the fuse 122. The comparison logic 126 compares the output signal of the fuse latch 124 with a column address CA<0:n> applied at present.
Herein, since the fuse 122, the fuse latch 124, and the comparison logic 126 are widely known typical circuit blocks, their internal circuits are not described.
If any, since the comparison logic 126 requires the input of the column address CA<0:n> applied at present, global lines for transferring the column address CA<0:n> to the comparison logic 126 need to be arrayed. FIG. 1 shows a case where four global address line sets are arrayed. Each global address line set includes global line addresses as many as the number (n+1) of bits of the column address CA<0:n>, the total number of global address lines is great.
Therefore, a global address line driver 130 for driving the global address lines drives a great deal of loading. When it is assumed that the loading for one global address line set is referred to as ‘Cr’, the loading that the global address line driver 130 has to drive reaches approximately ‘4Cr’. Such a great load negatively affects the high-speed operation of a semiconductor memory device.
Meanwhile, as mentioned above, since there are many global address lines, there is a problem in that the size of a chip for routing the global address lines is great.
As a semiconductor integrated circuit is integrated higher and higher, more redundant column lines are needed. Accordingly, the number of needed global address lines is increased as many as the number of the redundant column lines. Therefore, the loading problem from the global address lines and the chip size problem are expected to become more serious.